发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND REPAIR METHOD THEREOF |
摘要 |
A semiconductor memory device is provided which includes a memory cell group and a fuse cell group including at least one fuse cell to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to replace the defective memory cell included in the memory cell group; a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line; a fuse sense amplifier configured to read the failed address in response to the activation of the word line; and a repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell. |
申请公布号 |
US2015003141(A1) |
申请公布日期 |
2015.01.01 |
申请号 |
US201414220275 |
申请日期 |
2014.03.20 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
SON Jong-Pil;PARK Chul-Woo;SOHN Young-Soo |
分类号 |
G11C29/00;G11C11/407;G11C17/16 |
主分类号 |
G11C29/00 |
代理机构 |
|
代理人 |
|
主权项 |
1. A semiconductor memory device, comprising:
a row decoder; a memory cell group coupled to the row decoder by a word line, the memory cell group including a plurality of memory cells; a fuse cell group coupled to the row decoder by the word line, the fuse cell group including at least one fuse cell configured to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to replace the defective memory cell in the memory cell group; a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line; a fuse sense amplifier configured to read the failed address in response to the activation of the word line; and a repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell. |
地址 |
Suwon-si KR |