发明名称 Prefetch optimization in shared resource multi-core systems
摘要 An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced. Yet, if prefetch accuracy is low—miss rate is high—then more prefetch throttling is needed to save power, because the prefetch are not being utilized—performance is not being enhanced by the large number of prefetches.
申请公布号 US8924651(B2) 申请公布日期 2014.12.30
申请号 US201313864028 申请日期 2013.04.16
申请人 Intel Corporation 发明人 Tang Perry P.;Rotithor Hemant G.;Carlson Ryan L.;Aboulenein Nagi
分类号 G06F12/00;G06F12/08;G06F15/80 主分类号 G06F12/00
代理机构 Baker Botts L.L.P. 代理人 Baker Botts L.L.P.
主权项 1. An apparatus comprising: a processor core; and prefetch throttling logic associated with the processor core, the prefetch throttling logic to: determine a congestion bandwidth amount;determine a prefetch accuracy;determine whether the congestion bandwidth amount is less than a low congestion bandwidth threshold;set a prefetch throttling level of a number of throttling levels to zero in response to a determination that the congestion bandwidth amount is less than the low congestion bandwidth threshold; andprovide the prefetch throttling level to the processor core based on the bandwidth congestion and the prefetch accuracy.
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