发明名称 |
CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OPTIMIZATION |
摘要 |
Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode. |
申请公布号 |
WO2014193998(A1) |
申请公布日期 |
2014.12.04 |
申请号 |
WO2014US39856 |
申请日期 |
2014.05.28 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
SHAH, JAY MADHUKAR;SWAMYNATHAN, CHETHAN;DATTA, ANIMESH |
分类号 |
G01R31/3185 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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