Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions

摘要

A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.

主权项

1. A method of executing instructions in an instruction stream comprising:
receiving a first instruction of the instruction stream, the first instruction utilizing a respective address as a target address; in response to determining that a second instruction occurring later than the first instruction in the instruction stream utilizes the respective address as a target address without the respective address being utilized as a source address between the first instruction and the second instruction, decoding a first opcode identified by the second instruction to change the first opcode to a second opcode for the second instruction that is different from the first opcode.