发明名称 Transaction-based shared memory protection for high availability environments
摘要 Various systems and methods for implementing a transaction-based shared memory protection for high availability environments are described herein. A processing thread is executed, with the processing thread configured to access a multi-stage critical section, the multi-stage critical section having a first and second stage, the first stage to store a staging area of a plurality of operations to be executed in the memory shared with at least one other processing thread, and the second stage to execute the operations from the staging area. The thread further configured to determine whether the staging area includes an indication of successfully completing the first stage and execute the operations when there is an indication of successfully completing the first stage.
申请公布号 US8893137(B2) 申请公布日期 2014.11.18
申请号 US201213419232 申请日期 2012.03.13
申请人 Cisco Technology, Inc. 发明人 Therrien Paul Jacques
分类号 G06F9/46;G06F9/52 主分类号 G06F9/46
代理机构 代理人
主权项 1. A machine-readable medium comprising instructions for thread recovery in a multi-threaded environment with at least one thread operating on memory shared with at least one other thread, the instructions when executed on a computing device, cause the computing device to: execute a thread, wherein the thread is configured to: access a multi-stage critical section, the multi-stage critical section having a first and second stage, the first stage to store in a staging area a plurality of operations to be executed in the memory shared with at least one other thread, and the second stage to execute the operations from the staging area;determine whether the staging area includes an indication of successfully completing the first stage;execute the operations when there is an indication of successfully completing the first stage; andreset the staging area when there is no indication of successfully completing the first stage to ensure no stale entries exist before it is used; wherein the instructions to access the multi-stage critical section comprise instructions to: read a reference to the staging area from a memory location; anddereference the reference to access the staging area.
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