发明名称 Mechanisms to accelerate transactions using buffered stores
摘要 In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
申请公布号 US8886894(B2) 申请公布日期 2014.11.11
申请号 US201213658264 申请日期 2012.10.23
申请人 Intel Corporation 发明人 Adl-Tabatabai Ali-Reza;Ni Yang;Saha Bratin;Bassin Vadim;Sheaffer Gad;Callahan David;Gray Jan
分类号 G06F12/16 主分类号 G06F12/16
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. At least one non-transitory machine-readable medium comprising one or more instructions that when executed by a processor: during execution of a transactional memory (TM) transaction, store data at a location of a block stored in a cache memory of the processor if the block is present in the cache memory, using a user-level buffered store instruction to store the data, wherein the user-level buffered store instruction enables the data to be stored in the cache memory but not to be later written to a system memory; otherwise store the data at a first location, and store an address of the first location of the stored data in a write log; and acquire a write monitor for the block at commitment of the TM transaction and commit the TM transaction if no data in the write monitored block was lost.
地址 Santa Clara CA US