发明名称 |
Memory devices, systems and methods employing command/address calibration |
摘要 |
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. |
申请公布号 |
US8879342(B2) |
申请公布日期 |
2014.11.04 |
申请号 |
US201414295320 |
申请日期 |
2014.06.03 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Jeon Young-Jin |
分类号 |
G11C7/00;G11C8/06;G11C8/18;G11C7/22;G11C7/10 |
主分类号 |
G11C7/00 |
代理机构 |
Muir Patent Consulting, PLLC |
代理人 |
Muir Patent Consulting, PLLC |
主权项 |
1. A method of interface training, comprising:
sending a first calibration signal to a semiconductor device over a command/address bus; sending a clock signal to the semiconductor device with the sending of the first calibration signal, the clock signal providing a timing to the semiconductor device to latch logic levels of the first calibration signal; receiving a second calibration signal from the semiconductor device over a data bus, the second calibration signal being derived from latched logic levels of the first calibration signal; sending command and address signals over the command/address bus to the semiconductor device with the sending of the clock signal, a phase between the command and address signals and the clock signal being responsive to the second calibration signal. |
地址 |
Samsung-ro, Yeongtong-gu, Suwon-si KR |