发明名称 |
Semiconductor device |
摘要 |
The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal. |
申请公布号 |
US8872564(B2) |
申请公布日期 |
2014.10.28 |
申请号 |
US201313769000 |
申请日期 |
2013.02.15 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Uchiki Hideki;Kishimoto Satoru |
分类号 |
G06F1/04;H03K3/00;H03K17/687;H03K19/003;H03K17/56 |
主分类号 |
G06F1/04 |
代理机构 |
McDermott Will & Emery LLP |
代理人 |
McDermott Will & Emery LLP |
主权项 |
1. A semiconductor device comprising:
an input node that receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby; a detection unit that sets an enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period; and a signal transmission unit that includes P-channel MOS transistors and transmits a signal input to the input node according to control by the enable signal, wherein the signal transmission unit comprises: a first NAND circuit with one input coupled to the input node and the other input coupled to an output of the detection unit; and a second NAND circuit with one input coupled to an output of the first NAND circuit and the other input coupled to the output of the detection unit. |
地址 |
Kanagawa JP |