CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING THEREOF

摘要

A clock synchronization circuit including a delay locked loop and a semiconductor memory device comprising the same are disclosed. The clock synchronization circuit, according to an embodiment of the present invention, comprises: a delay locked loop for generating an output clock by delaying an input clock and locking the input clock and the output clock by performing the delay locking operation; and a delay lock controller for terminating the delay locking operation by determining whether the locking state of the delay locked loop is maintained.