| 主权项 |
1. A method of manufacturing an integrated circuit package, comprising:
providing a carrier substrate having a planar surface; forming a grid frame on the planar surface of the carrier substrate, the grid frame having a plurality of openings therein; placing a plurality of semiconductor device dies active-side down at laterally spaced-apart locations as defined by locations of the grid frame openings on the planar surface; covering the semiconductor device dies with a mold compound to form laterally spaced-apart mold sub-arrays on the planar surface; and curing the laterally spaced-apart mold sub-arrays, wherein the semiconductor device dies are retained at substantially the same laterally spaced-apart locations on the planar surface after the curing, and adjacent ones of the mold sub-arrays are each separated by a gap having a separation distance that is a value in a range from about 2 microns to about 10 microns and wherein the gap is occupied by a portion of the grid frame. |
