| 摘要 |
This semiconductor memory device comprises: a memory cell array including plural bit lines, plural word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plural bit lines and the plural word lines; and a control unit operative to control a voltage applied to the bit line and the word line. The control unit, when performing a certain operation consecutively on a plurality of the memory cells, selects a first bit line selected from among the plural bit lines and a first word line selected from among the plural word lines to perform a first operation on a first memory cell. Then, in a subsequent second operation following this first operation, selects a second bit line different from the first bit line and a second word line different from the first word line to select a second memory cell. |
| 主权项 |
1. A semiconductor memory device, comprising:
a memory cell layer including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, respectively; and a control unit configured to control a voltage applied to the bit line and the word line, each of the memory cells including a variable resistance element and a non-ohmic element, and wherein the control unit being configured to, when performing an operation consecutively on a plurality of the memory cells, select a first bit line selected from among the plurality of bit lines and a first word line selected from among the plurality of word lines to perform a first operation on a first memory cell, and then, in a subsequent second operation following the first operation, select a second bit line different from the first bit line and a second word line different from the first word line to select a second memory cell. |
