发明名称 Voltage regulator
摘要 A voltage regulator has a phase compensation circuit which changes consumption current according to load current thereby to reduce consumption current. The phase compensation circuit includes: a first transistor having a drain connected to an output terminal of an error amplifier circuit; a second transistor having a drain connected to a gate of the first transistor and a gate connected to the gate of the first transistor; a current mirror circuit connected to the output terminal of the error amplifier circuit, a drain of the first transistor, and the drain of the second transistor; and a capacitor connected between the gate of the second transistor and a drain of an output transistor. Thereby, current consumed by the phase compensation circuit can be changed according to the load current, resulting in that the voltage regulator consumes less current.
申请公布号 US8866457(B2) 申请公布日期 2014.10.21
申请号 US201213564876 申请日期 2012.08.02
申请人 Seiko Instruments Inc. 发明人 Endo Daiki;Heng Socheat
分类号 G05F1/575 主分类号 G05F1/575
代理机构 Brinks Gilson & Lione 代理人 Brinks Gilson & Lione
主权项 1. A voltage regulator comprising: an error amplifier circuit which amplifies and outputs the difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor so as to control a gate of the output transistor; and a phase compensation circuit, wherein the phase compensation circuit comprises: a first transistor having a drain thereof connected to an output terminal of the error amplifier circuit;a second transistor having a drain thereof connected to a gate of the first transistor and a gate thereof connected to the gate of the first transistor through a resistor;a current mirror circuit which comprises a voltage detector transistor detecting a voltage input to the gate of the output transistor, mirrors current flowing into the voltage detector transistor and supplies current to a drain of the first transistor and a drain of the second transistor; anda first capacitor connected between a gate of the second transistor and a drain of the output transistor.
地址 Chiba JP