发明名称 |
Memory device having buried bit line and vertical transistor and fabrication method thereof |
摘要 |
A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. |
申请公布号 |
US8865550(B2) |
申请公布日期 |
2014.10.21 |
申请号 |
US201414184725 |
申请日期 |
2014.02.20 |
申请人 |
Nanya Technology Corp. |
发明人 |
Wu Tieh-Chiang;Chen Yi-Nan;Liu Hsien-Wen |
分类号 |
H01L21/66;H01L29/66;H01L27/108;H01L29/78;H01L21/225 |
主分类号 |
H01L21/66 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. A method of forming a buried bit line, comprising:
providing a substrate, wherein a line-shaped trench region is defined in the substrate; forming a line-shaped trench in the line-shaped trench region of the substrate, wherein the line-shaped trench comprises a sidewall surface and a bottom surface; widening the bottom surface of the line-shaped trench to form a curved bottom surface in the line-shaped trench; forming a doping area in the substrate adjacent to the curved bottom surface; and forming a buried conductive layer on the doping area such that the buried conductive layer forms the buried bit line, wherein the step of forming the buried conductive layer comprises: depositing a metal layer into the line-shaped trench; removing the doping area and the metal layer in the line-shaped trench region; and filling the line-shaped trench with an insulation material. |
地址 |
Kueishan, Tao-Yuan Hsien TW |