| 发明名称 |
Clocked memory with latching predecoder circuitry |
| 摘要 |
A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results. |
| 申请公布号 |
US8861301(B2) |
申请公布日期 |
2014.10.14 |
| 申请号 |
US201213491712 |
申请日期 |
2012.06.08 |
| 申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Ramamurthy Hema;Ramaraju Ravindraraj |
| 分类号 |
G11C8/00;G11C8/10 |
主分类号 |
G11C8/00 |
| 代理机构 |
|
代理人 |
Clingan, Jr. James L.;Chiu Joanna G. |
| 主权项 |
1. A memory, comprising:
a memory array having a plurality of word lines; a plurality of latching predecoders, wherein each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the clock cycle of the clock signal, wherein, in response to the second edge, every latching predecoder of the plurality of latching predecoders provides a same predetermined value; and word line driver logic coupled to the plurality of latching predecoders which selectively activates a selected word line of the plurality of word lines in response to the latched results. |
| 地址 |
Austin TX US |
