发明名称 Network processor architecture
摘要 A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.
申请公布号 US8861344(B2) 申请公布日期 2014.10.14
申请号 US201012819587 申请日期 2010.06.21
申请人 Bay Microsystems, Inc. 发明人 Trinh Man D.;Bleszynski Ryzsard;Lee Barry T.;Chen Steve C.;Yang Eric K.;Chong Simon S.;Chiang Tony J.;Tsong Jun-Wen;Ono Goichiro;Gershman Charles F.
分类号 H04L12/56;H04L12/54;G06F15/00;G06F17/00;G06F9/38;H04L12/815;H04L12/801;H04L12/863;H04L12/28 主分类号 H04L12/56
代理机构 代理人
主权项 1. A traffic processor for scheduling information elements for forwarding, wherein each information element is associated with a flow and comprises at least one information element segment, the traffic processor comprising: multiple shapers, each shaper associated with an egress port and at least one flow of information elements, wherein each shaper is governed by at least one quality of service (“QoS”) parameter; multiple groups, wherein each group includes multiple shapers; a group arbiter for arbitrating among the multiple groups to select a group; a shaper arbiter for arbitrating among the multiple shapers within the selected group to select a shaper; and a scheduler for scheduling for forwarding an information element segment associated with the selected shaper; wherein each port is associated with only a subgroup of shapers within a group, and the shapers within the subgroup are arbitrated together during shaper arbitration.
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