发明名称 Booster circuit, semiconductor device and electronic apparatus
摘要 A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current. The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased.
申请公布号 US8847673(B2) 申请公布日期 2014.09.30
申请号 US201313936401 申请日期 2013.07.08
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kimura Hajime
分类号 G05F1/10;G11C5/14;H02M3/07 主分类号 G05F1/10
代理机构 Husch Blackwell LLP 代理人 Husch Blackwell LLP
主权项 1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a first capacitor; a second capacitor; and a third capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to a first terminal of the second capacitor, wherein a gate of the first transistor is electrically connected to a first terminal of the first capacitor, wherein one of a source and a drain of the second transistor is electrically connected to the first terminal of the first capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to the first terminal of the second capacitor, wherein a gate of the second transistor is electrically connected to a second terminal of the second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a first terminal of the third capacitor, wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring or the first terminal of the second capacitor, wherein a gate of the third transistor is electrically connected to the second terminal of the second capacitor, wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring, wherein the other of the source and the drain of the fourth transistor is electrically connected to the first terminal of the second capacitor, wherein a gate of the fourth transistor is electrically connected to the first terminal of the third capacitor, and wherein a second terminal of the first capacitor is electrically connected to a second terminal of the third capacitor.
地址 JP