发明名称 |
High electron mobility transistor and method of forming the same |
摘要 |
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. |
申请公布号 |
US8841703(B2) |
申请公布日期 |
2014.09.23 |
申请号 |
US201113297525 |
申请日期 |
2011.11.16 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wong King-Yuen;Yu Chen-Ju;Yao Fu-Wei;Hsu Chun-Wei;Yu Jiun-Lei Jerry;Hsiung Chih-Wen;Yang Fu-Chih |
分类号 |
H01L29/66;H01L29/51;H01L29/778;H01L29/207;H01L29/20 |
主分类号 |
H01L29/66 |
代理机构 |
Lowe Hauptman & Ham, LLP |
代理人 |
Lowe Hauptman & Ham, LLP |
主权项 |
1. A semiconductor structure comprising:
a first III-V compound layer; a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, wherein a fluorine region is embedded in the second III-V compound layer under the gate electrode; a gate dielectric layer disposed over the second III-V compound layer, the gate dielectric layer having a fluorine segment on the fluorine region and under at least a portion of the gate electrode, wherein the gate dielectric layer extends over a top surface of the source feature and the drain feature; and a dielectric cap layer, the dielectric cap layer underlying a portion of the gate dielectric layer and overlying the second III-V compound layer. |
地址 |
TW |