Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor

摘要

The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.

主权项

1. A method for manufacturing a transistor, comprising:
defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously; wherein the step of forming the semiconductor spacer surrounding the primary spacer and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other further comprises: forming an etch-stop layer on the surfaces of the source/drain regions and the primary spacer; forming a semiconductor layer on a surface of the etch-stop layer; etching the semiconductor layer to form the semiconductor spacer surrounding the primary spacer; removing the ends of the semiconductor spacer in the width direction of the gate by etching to avoid electrical conduction between the source/drain regions; and removing an exposed portion of the etch-stop layer.