| 摘要 |
<p>A memory mat (101) is configured to have a main unit portion (200) which has first capacitors (203A), a linear conductive film (204) formed between the main unit portion (200) and peripheral circuitry (104), and a second capacitor (203B) which is formed such that the linear conductive film (204) and a lower portion come into contact, said first capacitor (203A) being formed such that a contact layer (202) and the lower portion come into contact.</p> |
