发明名称 FMCW RADAR LEVEL GAUGE WITH LOCK STATE CONTROL
摘要 The present invention relates to a radar level gauge system comprising PLL circuitry for generating an output signal. The PLL circuitry is configured to indicate a lock state of the PLL circuitry; and signal modifying circuitry is connected to the PLL circuitry for receiving the output signal and for modifying at least one property of the output signal for forming the transmit signal. The signal modifying circuitry is arranged and configured to receive a PLL status signal indicative of the lock state of the PLL circuitry, and to modify the at least one property of the output signal in response to the PLL status signal indicating that the PLL circuitry is in a locked state.
申请公布号 US2014253147(A1) 申请公布日期 2014.09.11
申请号 US201313788700 申请日期 2013.03.07
申请人 Rosemount Tank Radar AB 发明人 Kleman Mikael;Jirskog Anders
分类号 G01B7/26;G01B15/00 主分类号 G01B7/26
代理机构 代理人
主权项 1. A radar level gauge system for determining a filling level of a product in a tank, comprising: a transceiver for generating, transmitting and receiving electromagnetic signals; a signal propagation device coupled to the transceiver for propagating a transmit signal towards a surface of said product, and for propagating a surface echo signal resulting from reflection of said transmit signal at said surface back towards said transceiver; and processing circuitry coupled to said transceiver for determining said filling level based on a relation between said transmit signal and said surface echo signal, said transceiver comprising: PLL circuitry for generating an output signal, said PLL circuitry being configured to indicate a lock state of said PLL circuitry; and frequency modifying circuitry connected to said PLL circuitry for receiving said output signal and for increasing a frequency of said output signal to form said transmit signal, wherein said frequency modifying circuitry is controllable between a first state in which the frequency of said output signal is not increased by said frequency modifying circuitry, and a second state in which the frequency of said output signal is increased by said frequency modifying circuitry, and wherein said frequency modifying circuitry is arranged and configured to receive a PLL status signal indicative of said lock state of the PLL circuitry, and to transition from said first state to said second state in response to said PLL status signal indicating that said PLL circuitry is in a locked state.
地址 Goteborg SE