发明名称 Semiconductor storage device
摘要 A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.
申请公布号 US8830760(B2) 申请公布日期 2014.09.09
申请号 US201313771328 申请日期 2013.02.20
申请人 Kabushiki Kaisha Toshiba 发明人 Funatsuki Rieko;Nagao Osamu
分类号 G11C16/06;G11C16/34;G11C16/28;G11C7/14 主分类号 G11C16/06
代理机构 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A semiconductor storage device comprising: a plurality of memory cells; and a sense amplifier including a sense node that transmits a voltage according to a current flowing in a corresponding one of the memory cells and configured to detect a logic of data based on the voltage of the sense node, wherein a write sequence of writing data in a selected memory cell among the memory cells is performed by repeating write loops each including a write stage of writing data in the selected memory cell and a verify read stage of verifying that the data has been written in the selected memory cell by performing discharge from the sense node through the selected memory cell, and the sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop among the write loops, a period of discharge from the sense node to the selected memory cell at the verify read stage in a second write loop following the first write loop.
地址 Tokyo JP