Etch-back method for planarization at the position-near-interface of an interlayer dielectric

摘要

The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

主权项

1. A method for planarizing a stack structure constituted by a dielectric layers on a semiconductor structure, comprising:
performing a heat treatment on the stack structure to make it reflow; performing a first etching, until approaching an interlayer interface between the dielectric layers in the stack structure; and performing a second etching, until the top of the semiconductor structure is exposed, wherein etching rates of the second etching for the dielectric layers in the stack structure close to the interlayer interface are identical, wherein a distance between a stop position of the first etching and the interlayer interface of the stack structure is from 100 Å to 1,000 Å.