REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NON-VOLATILE MEMORY

摘要

A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

主权项

1. A method for reading, the method comprising:
performing a read operation for a selected memory cell in a first plurality of memory cells, the first plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, and the performing a read operation comprises applying a control gate voltage to a selected word line of the three-dimensional non-volatile memory which is coupled to the selected memory cell while providing a drain-side select gate of the first plurality of memory cells in a conductive state and while sensing a threshold voltage of the selected memory cell; and controlling a boosting level of a channel of an active area of a second plurality of memory cells during the read operation, the second plurality of memory cells are formed above the substrate in the multiple physical levels of memory cells in the three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory, the controlling comprises allowing boosting of the channel followed by interrupting boosting of the channel, the allowing boosting of the channel comprise applying an increasing pass voltage to an unselected word line of the three-dimensional non-volatile memory while providing select gates of the second plurality of memory cells in a non-conductive state, and the interrupting boosting of the channel comprises transitioning at least one of the select gates of the second plurality of memory cells from the non-conductive state to the conductive state, the performing of the read operation and the controlling of the boosting level are performed by circuitry which is associated with operation of the first plurality of memory cells and the second plurality of memory cells.