Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system

摘要

A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

主权项

1. An apparatus, comprising:
a bus including a plurality of signal lines configured to transmit; and a controller configured to serially provide a plurality of portions of data to the bus, a portion of data of the plurality of portions of data having fewer bits than a number of the plurality of signal lines of the bus, wherein the controller is further configured to provide additional information to the plurality of signal lines of the bus not utilized by the portion of data of the plurality of portions of data in parallel with the portion of the data of the plurality of portions of data.