Formal verification coverage metrics for circuit design properties

摘要

A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

主权项

1. A computer-implemented method for circuit design verification, comprising:
performing formal verification on a circuit design to prove a correctness of at least one property of the circuit design, the circuit design having a cone of influence representing a portion of the circuit design capable of affecting signals of the at least one property; identifying a proof core of the circuit design, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the at least one property; identifying, from a plurality of cover items, one or more cover items corresponding to the proof core; and generating, by a computer, a coverage metric that is indicative of a level of formal verification coverage provided by the at least one property during the formal verification based on a relationship between the one or more cover items corresponding to the proof core and the plurality of cover items, a lower coverage metric indicating that more properties are needed for sufficient verification coverage, and a higher coverage metric indicating that the at least one property provides sufficient verification coverage.