发明名称 |
Methods of forming a FinFET semiconductor device by performing an epitaxial growth process |
摘要 |
A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer. |
申请公布号 |
US8815659(B2) |
申请公布日期 |
2014.08.26 |
申请号 |
US201213716686 |
申请日期 |
2012.12.17 |
申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
Chi Min-hwa;Kim Nam Sung |
分类号 |
H01L21/84;H01L29/66;H01L29/78 |
主分类号 |
H01L21/84 |
代理机构 |
Amerson Law Firm, PLLC |
代理人 |
Amerson Law Firm, PLLC |
主权项 |
1. A method of forming a FinFET device comprised of at least one fin structure and a plurality of source/drain structures, the method comprising:
forming a masking layer having an initial thickness above a semiconducting substrate, said masking layer exposing a first exposed region of said semiconducting substrate where said at least one fin structure will be formed and a plurality of second exposed regions where said plurality of source/drain structures will be formed; with said masking layer in position, performing an epitaxial growth process to form a layer of semiconducting material on said first and second exposed regions of said semiconducting substrate to thereby form said at least one fin structure and said plurality of source/drain structures; performing a chemical mechanical planarization process to planarize an upper surface of said layer of semiconducting material with an upper surface of said masking layer; after performing said chemical mechanical planarization process, performing a process operation to reduce said initial thickness of said masking layer; forming a gate insulation layer around at least a portion of said at least one fin structure; and forming a gate electrode above said gate insulation layer. |
地址 |
Grand Cayman KY |