发明名称 |
High performance CMOS transistors using PMD liner stress |
摘要 |
A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent. |
申请公布号 |
US8809141(B2) |
申请公布日期 |
2014.08.19 |
申请号 |
US200711670192 |
申请日期 |
2007.02.01 |
申请人 |
Texas Instruments Incorporated |
发明人 |
Bu Haowen;Khamankar Rajesh;Grider Douglas T. |
分类号 |
H01L29/739 |
主分类号 |
H01L29/739 |
代理机构 |
|
代理人 |
Garner Jacqueline J.;Telecky, Jr. Frederick J. |
主权项 |
1. A method of forming an integrated circuit, comprising:
providing a semiconductor substrate; forming a gate dielectric layer on a surface of said semiconductor substrate; forming a first gate electrode over said gate dielectric layer for a PMOS device; forming a second gate electrode over said gate dielectric layer for an NMOS device; forming sidewall structures adjacent said first gate electrode and said second gate electrode; forming source and drain regions in said semiconductor substrate adjacent said sidewall structures; forming a high stress liner layer over the first gate electrode, the second gate electrode and the source and drain regions by:
forming a silicon nitride layer with a hydrogen concentration greater than 20 atomic percent and a first tensile stress over said first gate electrode, said second gate electrode, and said source and drain regions; andthermally annealing said silicon nitride layer before forming any additional layers on the silicon nitride layer, resulting in a second tensile stress greater than 800 mPa and a second hydrogen concentration greater than 12 atomic % in said silicon nitride layer for the PMOS device and the NMOS device thereby exerting a tensile stress in a channel region of the NMOS device, enhancing channel mobility for the NMOS device without substantially affecting channel mobility of the PMOS device; and forming a pre-metal dielectric (PMD) layer on the high stress liner layer after thermal annealing. |
地址 |
Dallas TX US |