发明名称 Multiprocessor system and multigrain parallelizing compiler
摘要 Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.
申请公布号 US8812880(B2) 申请公布日期 2014.08.19
申请号 US201012654956 申请日期 2010.01.11
申请人 Waseda University 发明人 Kasahara Hironori;Kimura Keiji;Shirako Jun;Ito Masaki;Shikano Hiroaki
分类号 G06F1/00;G06F9/50;G06F1/32;G06F9/45;G06F9/48 主分类号 G06F1/00
代理机构 Morris, Manning & Martin, LLP 代理人 Marquez Juan Carlos A.;Morris, Manning & Martin, LLP
主权项 1. A multiprocessor system having processor units that include a single type or a plurality of types of processors, the multiprocessor system comprising: a clock supply unit for supplying one of a plurality of clock frequencies as a system clock to each of the processor units; a power supply unit for supplying one of a plurality of voltages as a system voltage to each of the processor units; a respective local memory provided in each processor unit and arranged to store data or commands; a shared memory accessed by the processor units; a local bus connecting the shared memory to the processor units; and a respective system control register provided in each processor unit for setting the system clock and the system voltage to be supplied to the processor and the respective local memory in the processor unit, wherein the respective system control register in each processor unit includes bit fields that respectively store values of clock frequencies and system voltages to be set for elements in the processor unit, and wherein the respective system control register in each processor unit is assigned an address to access the system control register, and furthermore each bit field of each respective system control register is assigned a respective individual address to allow direct access to each bit field and the values stored in each bit field by another processor unit.
地址 Tokyo JP
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