发明名称 |
IMAGE DISPLAY DEVICE AND DRIVING METHOD |
摘要 |
Data lines are connected to pixels arranged on both sides of the data lines respectively, a cth gate line and a (c+1)th gate line are connected respectively to pixels arranged between the cth gate line and the (c+1)th gate line alternately, in the case of displaying an image at a Nth frame, the first gate line driver circuit and the second gate line driver circuit supply the gate signal to the cth gate line and the (c+1)th gate line in this order, and in the case of displaying an image at a (N+1)th frame, the first gate line driver circuit and the second gate line driver circuit supply the gate signal to the (c+1)th gate line and the cth gate line in this order. |
申请公布号 |
US2014225819(A1) |
申请公布日期 |
2014.08.14 |
申请号 |
US201414171053 |
申请日期 |
2014.02.03 |
申请人 |
Japan Display Inc. |
发明人 |
ONUMA Takahiro;Harada Kenji;Maruyama Satoshi |
分类号 |
G09G3/36;G09G3/20 |
主分类号 |
G09G3/36 |
代理机构 |
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代理人 |
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主权项 |
1. An image display device comprising:
an image display unit on which (C×2D) pixels are arrayed in a matrix pattern; D data lines configured to supply data signals to the pixels; 2C gate lines arranged so as to intersect the data lines and configured to supply gate signals to the pixels; a data line driver circuit configured to supply data signals to the data lines; a first gate line driver circuit configured to supply gate signals to a cth gate line (where c is an odd number and a relation 1≦c<2C−1 is satisfied); and a second gate line driver circuit configured to supply gate signals to a (c+1)th gate line, wherein the data lines are connected to the pixels arranged on both sides of the data lines respectively, the cth gate line and the (c+1)th gate line are connected respectively to the pixels arrayed between the cth gate line and the (c+1)th gate line alternately, and the first gate line driver circuit and the second gate line driver circuit (1) supplies the gate signals to the cth gate line and the (c+1)th gate line in this order when displaying an image at the Nth frame (N≧1), and (2) supplies the gate signals to the (c+1)th frame and the cth gate line in this order when displaying an image at a (N+1)th frame. |
地址 |
Minato-ku JP |