发明名称 METHOD FOR FORMING SILICON/GERMANIUM CONTAINING DRAIN/SOURCE REGIONS IN TRANSISTORS WITH REDUCED SILICON/GERMANIUM LOSS
摘要 By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.
申请公布号 KR101428766(B1) 申请公布日期 2014.08.08
申请号 KR20097018206 申请日期 2008.01.31
申请人 发明人
分类号 H01L21/336;H01L29/78 主分类号 H01L21/336
代理机构 代理人
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