Partial reconfiguration circuitry

摘要

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.

主权项

1. An integrated circuit comprising:
an array of memory elements; and partial reconfiguration circuitry that is coupled to the array of memory elements, wherein the partial reconfiguration circuitry comprises:
a control circuit; anddata register circuitry that stores data that is read from a selected row of memory elements in the array of memory elements and to modify the read data to produce modified data, wherein the control circuit loads the modified data from the data register circuitry into the selected row of memory elements in the array of memory elements, wherein the control circuit includes a configurable logic circuit that produces the modified data by using the configurable logic circuit to implement a logic function selected from the group consisting of: a logic AND function, a logic OR function, a logic XOR function, a logic NAND function, a logic NOR function, and a logic XNOR function.