Methods and Systems for Chip-to-Chip Communication with Reduced Simultaneous Switching Noise

摘要

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

主权项

1. A system for interconnection of a memory controller device and at least one memory device using a vector signaling code to communicate binary data, the system comprised of:
a collection of interconnection wires from the memory controller device to the at least one memory device, the wires having essentially identical transmission characteristics, a transmission interface to the collection of interconnection wires in each of the memory controller device and at least one memory device, a reception interface to the collection of interconnection wires in each of the memory controller device and at least one memory device, an encoding of the binary data to a vector signaling code word of three or more levels in the transmission interface, communication of the vector signaling code word in one transmission interval from the transmission interface over the collection of interconnection wires to at least one reception interface, a decoding of the vector signaling code to binary output data in the reception interface, wherein at least one of the simultaneous switching output noise and the transmission interface power consumption is reduced in comparison to transmission of the binary data over the same collection of interconnection wires.