| 摘要 |
The present invention relates to a latency control circuit and a semiconductor memory device including the same, including an internal command generating unit for generating an internal command in response to an external command; a clock delay unit for delaying an external clock by an operation delay amount of the internal command generating unit and generating an internal clock; a command synchronization unit for synchronizing the internal command sequentially with the internal clock and the external clock for compensating the operation delay amount of the internal commend generating unit and generating a synchronization command; and a latency shifting unit for shifting the synchronization command by the number of set latency on the basis of the external clock. |
