发明名称 System for providing trace data in a data processor having a pipelined architecture
摘要 The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention including providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions are complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of the trace output buffer.
申请公布号 US8775875(B2) 申请公布日期 2014.07.08
申请号 US200912387152 申请日期 2009.04.28
申请人 Imagination Technologies, Limited 发明人 Isherwood Robert Graham;Oliver Ian;Webber Andrew
分类号 G06F11/34 主分类号 G06F11/34
代理机构 代理人 Garrabrants Michael S.
主权项 1. A method of providing trace data from a data processor, the data processor including a scheduler for scheduling instructions to be executed by the data processor and a trace unit including a trace output buffer for storing trace data prior to output of the trace data to an external device, comprising: sending an indication of space available in the trace output buffer to the scheduler; pausing the scheduling of instructions based on the indication of space available; and including in the trace data the number of cycles for which the scheduling of instructions has been paused.
地址 Kings Langley, Hertfordshire GB