COLLAPSING OF MULTIPLE NESTED LOOPS, METHODS AND INSTRUCTIONS

摘要

In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

主权项

1. A processor comprising:
at least one core to execute instructions, the at least one core including a scalar unit and a vector unit, wherein the vector unit is to access a multi-dimensional loop counter stored in a vector storage of the processor, the multi-dimensional loop counter including a plurality of loop counters each of a loop of a nested loop formed a plurality of loops.