| 发明名称 |
SYSTEM AND METHOD FOR DETERMINATION OF LATENCY TOLERANCE |
| 摘要 |
Particular embodiments described herein can offer a method that includes receiving first link state information associated with a first device, determining, by a processor, an upward latency tolerance based, at least in part, on the first link state information, and providing the upward latency tolerance to a power management controller. |
| 申请公布号 |
US2014181334(A1) |
申请公布日期 |
2014.06.26 |
| 申请号 |
US201213726481 |
申请日期 |
2012.12.24 |
| 申请人 |
Jeyaseelan Jaya L.;Walsh Jim;Songer Neil;Cooper Barnes |
发明人 |
Jeyaseelan Jaya L.;Walsh Jim;Songer Neil;Cooper Barnes |
| 分类号 |
G06F13/10 |
主分类号 |
G06F13/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method to determine a latency tolerance, comprising:
receiving first link state information associated with a first device; determining an upward latency tolerance based, at least in part, on the first link state information; and providing the upward latency tolerance to a power management controller. |
| 地址 |
Cupertino CA US |
