发明名称 Semiconductor device test method and semiconductor device
摘要 A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.
申请公布号 US8754667(B2) 申请公布日期 2014.06.17
申请号 US201113035581 申请日期 2011.02.25
申请人 Fujitsu Semiconductor Limited 发明人 Mimura Chiaki;Shimabayashi Kazuhiko
分类号 G01R31/26 主分类号 G01R31/26
代理机构 Fujitsu Patent Center 代理人 Fujitsu Patent Center
主权项 1. A semiconductor device test method, comprising: performing a determination test of a test object circuit of the semiconductor device divided into a plurality of circuit blocks, while changing a scale of concurrently operating circuit blocks in the plurality of circuit blocks; detecting a power supply noise generated in the semiconductor device during performance of the determination test; determining a scale of the circuit blocks that an operation test is performed successfully based on a result of the determination test that was performed and the power supply noise that was detected; and performing the operation test on the test object circuit by controlling clocks to be supplied to the circuit blocks so that the scale of concurrently operating circuit blocks does not exceed the scale of the circuit blocks that was determined.
地址 Yokohama JP