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1. An apparatus comprising:
a memory cell array including a memory cell configured to be coupled to a bit line; a control circuit configured to provide a control signal; a voltage generator configured to provide a sense signal and a precharge signal in response to the control signal; and a page buffer configured to provide, in a single step, a bit line voltage to the bit line based on the sense signal and the precharge signal to control a programming of the memory cell, a value of the bit line voltage to be selected based on program data, the buffer including a
program unit including a data latch unit configured to store first data, anda non-program unit configured to store second data, the combination of the first data and the second data forming the program data, the non-program unit being further configured to
provide a bias voltage as the bit line voltage based on the program data, andincrease the bias voltage based on the program data.
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