PARALLEL-SERIAL CONVERSION CIRCUIT, INTERFACE CIRCUIT, AND CONTROL DEVICE

摘要

A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.