发明名称 SCHALTUNGSANORDNUNG MIT EINER ZYKLISCH ARBEITENDEN ZAEHLSTUFE UND EINER NACHGESCHALTETEN KONVERTERSTUFE.
摘要 An input value is generated (G) as a plus or minus value (+-X) that is entered into a counting circuit (Z) that has a memory stage (S) and a pair of adder circuits (A1,A2). The entered value is processed by the first stage that generates a value for a converter (V) that also provides an input to the second adder. Signals produced (L1,L2) indicate when the value has exceeded or become less than threshold values. The output generated by the converter is used as a correction value for the contents of the memory. Output is converted into 7 segment form (M) for display.
申请公布号 DE3870538(D1) 申请公布日期 1992.06.04
申请号 DE19883870538 申请日期 1988.07.29
申请人 SIEMENS AG, 8000 MUENCHEN, DE 发明人 WETZEL, DIPL.-ING. (FH), FRIEDRICH, W-8551 HEROLDSBACH, DE;NICKEL, DIPL.-ING., ECKHARD, W-8552 HOECHSTADT, DE
分类号 G06F7/72;H03M7/18;(IPC1-7):G06F7/72 主分类号 G06F7/72
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