| 摘要 |
Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L≰k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus. |
