Method and apparatus for efficiently inserting fills in an integrated circuit layout

摘要

A method for efficiently producing a design layout that includes several fills between and around nets of the design layout is described. The method of some embodiments first places a set of fills in the design layout. The method then performs a timing analysis on the design layout to find out the impact of the fills on the timing of the nets. The method identifies a region of the design layout in which to trim a set of fills in order to fix any timing violations of the nets. The method then trims the set of fills in the identified region. In some embodiments, the method employs different trimming strategies for trimming fills around different nets based on the characteristics of the nets.