发明名称 |
Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing |
摘要 |
Preprocessing parallel sequences of“wait”statements and synthesizing these multiple“wait”statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer. |
申请公布号 |
US8713494(B2) |
申请公布日期 |
2014.04.29 |
申请号 |
US201313917638 |
申请日期 |
2013.06.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOBOK GABOR;DRASNY GABOR;EL-ZEIN ALI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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