SEMICONDUCTOR MEMORY DEVICE AND DEVICES HAVING THE SAME

摘要

A semiconductor memory device according to the present invention includes: multiple memory cells arranged on the area wherein multiple bit-line pairs and word-lines are intersecting; and a noise distribution circuit connecting to the memory cells corresponding to respective bit-line pairs among the bit-line pairs through the bit-line pairs. The noise distribution circuit discharges the bit-lines corresponding to half-selected memory cells or the complementary bit-lines upon performing a read or write operation of the memory cells selected from the multiple memory cells.