发明名称 |
Extracting capacitance and resistance from FinFET devices |
摘要 |
Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design. |
申请公布号 |
US8701066(B1) |
申请公布日期 |
2014.04.15 |
申请号 |
US201213655413 |
申请日期 |
2012.10.18 |
申请人 |
CADENCE DESIGN SYSTEMS, INC.;CADENCE DESIGN SYSTENS, INC. |
发明人 |
LO CHI-YUAN;KHAPAEV MIKHAIL |
分类号 |
G06F17/50;G06F17/11 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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