发明名称 ELECTRONIC APPARATUS
摘要 PROBLEM TO BE SOLVED: To prevent erroneous detection of abnormalities in a RAM.SOLUTION: A timer 30 measures an interpulse time T1 of a pulse signal from a velocity sensor 10, and outputs a start signal to a DMAC 28 at a timing of the rising of the pulse signal. The DMAC 28 transfers the interpulse time T1 to a prescribed address 27, and outputs a DMA transfer completion interruption signal to a CPU 22 when a counter C indicates a specified value Cset. The CPU 22 performs abnormality diagnosis of the inspection object address by performing processing for avoiding the inspection object address value, processing for writing and reading inspection data, restoration processing for returning the avoided data to the inspection object address and abnormality determination processing. In this case, a necessary time T2 for processing that is required for a period to completion of restoration processing by the CPU 22 after an output of the start signal to the DMAC 28 is adjusted to be smaller than the minimum value of the interpulse time T1. This can prevent erroneous detection of the abnormalities.
申请公布号 JP2014048920(A) 申请公布日期 2014.03.17
申请号 JP20120191813 申请日期 2012.08.31
申请人 AISIN AW CO LTD 发明人 ISONO TAKEMICHI
分类号 G06F12/16;G06F13/28 主分类号 G06F12/16
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