| 摘要 |
A clock generation circuit 10 includes a resonant reactor connected with a half voltage supply point TV1, a resonant capacitor CL connected between a ground voltage supply point TVss and an output terminal TVout, a transistor MP1 connected between the resonant reactor Lr and the resonant capacitor CL, and a transistor MN1 connected with the output terminal TVout. In this configuration, signals in a wide range of frequencies can be output with low power consumption by adjusting the time when a clock signal phi1 applied to the gates of the transistors MP1 and MN1 is high. |
