| 摘要 |
The present invention relates to a semiconductor memory device supporting data width options. The semiconductor memory device supports a first data width option operation for selectively transmitting the data to a first or a second global data lines by receiving data through a first input pad, and a second data width option operation for transmitting the data to the first and the second global data lines which respectively correspond to the first input pad and a second input pad by receiving data through the first input pad and the second input pad. The semiconductor memory device includes a first driving unit and a second driving unit which receive and output each of data input through the first and the second input pads in the second data width option operation. A data transfer path from the second input pad to the second driving unit is disabled in the first data width option operation. [Reference numerals] (310_1) First buffering unit; (310_2) First alignment unit; (310_3) First delay unit; (310_4) First bus inverting unit; (310_5) First driving unit; (320_1) Second buffering unit; (320_2) Second alignment unit; (320_3) Second delay unit; (320_4) Second bus inverting unit; (320_5) Second driving unit; (330) Output path control unit |
