发明名称 |
Dual vertical channel transistor and fabrication method thereof |
摘要 |
A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body. |
申请公布号 |
US8653584(B2) |
申请公布日期 |
2014.02.18 |
申请号 |
US20100727265 |
申请日期 |
2010.03.19 |
申请人 |
RENN SHING-HWA;NANYA TECHNOLOGY CORP. |
发明人 |
RENN SHING-HWA |
分类号 |
H01L29/78 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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