| 摘要 |
<p>A macrocell is provided for use in logic circuits which is capable of being configured into any one of six different states so as to replicate an X-type output architecture, an L-type output architecture and a number of hybrid architectures which encompass features from one or both of these types. The macrocell receives input signals (PT0, PT1, PT2, and PT3) at multiplexers (52a, 52b, 52c, and 52d) and OR gate (53b). The multiplexers (52a, 52b, 52c, 52d, 56a, and 56b) are responsive to control signals (ACO, ACl) so as to configure the programmable macrocell in an x-type, b-type, or hybrid architecture.</p> |
